The present invention relates to self-synchronous FIFO (First-In First-Out) memory devices and, in particular, to a self-synchronous FIFO memory device equipped with a control circuit for transmitting an input signal or output signal of a self-synchronous signal control circuit that controls a FIFO memory device.
Logic circuits that perform pipeline data processing in synchronization with a clock are, normally, implemented as logic LSIs. These logic LSIs have been under year-by-year developments to high speed, larger scale, and further microfabrication, with elongation of wiring length and reduction in spacing between wirings, so that series resistance of wirings and parallel capacitance between other wirings have been increasing more and more.
For this reason, signal delay and waveform rounding have been becoming larger, the influence of which would vary depending on the length of wirings, i.e. interconnect lines. Unfortunately, however, it is difficult to uniformize the lengths of interconnect lines to all flip-flops arranged randomly on the overall chip, making it harder and harder to achieve the distribution of an in-phase single clock.
Avoiding this problem would involve, for example, generating a clock tree in which buffers are arranged in a multi-stage tree structure for implementing a constant delay for the overall chip, which would lead to an increase in cost. Therefore, under discussions are logic circuits having a self-synchronous pipeline that allows local synchronization between neighboring pipeline registers to be maintained and that eliminates the need for an in-phase single clock.
In this self-synchronous pipeline, when data transfer is temporarily halted at an output end of the pipeline for the reason that succeeding-stage device is in a state of being unable to receive output data from the pipeline or another reason, data transfer is forced to be halted chainedly toward an input end of the pipeline, followed by a standby state lasting until data transfer at the output end of the pipeline is enabled again.
During this process, data within the pipeline flowing normally at some intervals are brought more compact in their intervals, thus the pipeline showing an autonomous buffer capacity. However, when the case is beyond the buffer capacity, there would occur a state that data reception at the input end of the pipeline is temporarily disabled. In this case, it is desirable that a FIFO memory device be inserted into the pipeline to reinforce the buffer capacity.
FIG. 8 shows an example of a FIFO memory device utilizing autonomous buffer capacity of such a self-synchronous pipeline. In FIG. 8, a FIFO memory device 800 includes three self-synchronous data transmission lines 811, 812, 813, and these self-synchronous data transmission lines 811, 812, 813 include pipeline registers 801, 802, 803, respectively. As a result of this, the FIFO memory device 800 is enabled to hold a maximum of three pieces of data.
Also, the three self-synchronous data transmission lines 811, 812, 813 of the FIFO memory device 800 include self-synchronous signal control circuits 804, 805, 806, respectively. These three self-synchronous signal control circuits 804, 805, 806, while handshaking each other, feed clocks to the pipeline registers 801, 802, 803.
As shown above, the self-synchronous data transmission lines 811, 812, 813 are each made up of a set of one self-synchronous signal control circuit 804, 805, 806 and one pipeline register 801, 802, 803 which operates with a clock that the self-synchronous signal control circuit 804, 805, 806 feeds. As shown in FIG. 8, the self-synchronous data transmission lines 811, 812, 813 are connected in series, by which the FIFO memory device 800 is implemented.
Next, FIG. 9 shows one configuration example of one of the self-synchronous signal control circuits 804, 805, 806 in the FIFO memory device 800 of FIG. 8. As shown in FIG. 9, the self-synchronous signal control circuit includes a CI signal terminal 901, an RO signal terminal 902, a CP output terminal 903, a CO output terminal 904 and an RI input terminal 905, and further includes an RS flip-flops 906, 908 and a four-input NAND gate 907 which is a logic circuit.
A transfer request signal of the preceding stage is inputted to the CI signal terminal 901, and the RO signal terminal 902 returns to the preceding stage an acknowledge signal showing the reception of the transfer request signal from the CI signal terminal 901. Also, the CP signal terminal 903 transmits clock pulses to the pipeline registers 801 to 803 according to the transfer request signal from the CI signal terminal 901.
The CO output terminal 904 transfers the transfer request signal from the preceding stage to the succeeding stage. Also, to the RI signal terminal 905 is returned an acknowledge signal showing that the transfer request from the CO signal terminal 904 has been received by the succeeding stage. Further, the RS flip-flop 906 holds a transfer request acceptance state, while the RS flip-flop 908 holds a transfer request state for the succeeding stage. Further, the four-input NAND gate 907 maintains synchronization of the RS flip-flop 906 and the RS flip-flop 908.
Next, a timing chart of FIG. 10 shows an example of the signal for activating a self-synchronous pipeline partly composed of the FIFO memory device 800 of FIG. 8. A pulse of a transfer request signal 804CI is inputted to a CI signal terminal CI of the self-synchronous signal control circuit 804 forming the first stage of the pipeline in the FIFO memory device 800 of FIG. 8. Similarly, processing data 801D is inputted to a data terminal D of the first-stage pipeline register 801.
As a result, the RS flip-flop 906 for holding the transfer request acceptance state in the self-synchronous signal control circuit 804 is set, and an acknowledge signal 804RO is returned to the Self-synchronous signal control circuit of the preceding-stage FIFO memory device from an RO signal terminal RO of the self-synchronous signal control circuit 804. As a result of this, the transfer request signal 804CI returns to the H (High) level while a signal 804NAND goes L (Low) level, so that the RS flip-flop 908 for holding a transfer request to the succeeding stage is set and the RS flip-flop 906 is cleared.
Next, a clock 804CP for the pipeline register 801 goes H level, by which data is latched to the pipeline register 801 and this data is outputted to a terminal Q of the pipeline register 801. Also, a transfer request pulse 804CO for the succeeding stage is outputted from a terminal CO of the self-synchronous signal control circuit 804. This transfer request pulse 804CO is inputted to the self-synchronous signal control circuit 805 forming the second-stage self-synchronous data transmission line 812 composing the pipeline of FIG. 8. Likewise, a signal 804RI, a signal 805NAND, a signal 805CP and a signal 805CO are generated, and a signal 801Q is latched by the second-stage pipeline register 802 and outputted to the terminal Q.
Similar operations are performed between the self-synchronous signal control circuit 805 and the self-synchronous signal control circuit 806, by which a data signal 802Q is latched by the third-stage pipeline register 803 and outputted from the terminal Q of the pipeline register 803 to the data path output.
Meanwhile, a FIFO memory device intended for insertion into a self-synchronous pipeline has to be capable of processing asynchronous two requests of data write and read in parallel and moreover capable of processing at the same speed as the other parts of the self-synchronous pipeline.
Also, in the case where data is held in this FIFO memory device, a control mechanism for spontaneously generating a data transfer request is indispensable. Further, the FIFO memory device is expected to substantially increase the physical storage capacity without increasing the delay time that is simply proportional to the depth of the pipeline. Furthermore, in order to implement an optimum FIFO memory device for pipeline processing, it is desirable that the FIFO memory device can change the storage capacity dynamically and statically.
The above FIFO memory device 800 of the related art, in which the self-synchronous data transmission lines 811, 812, 813 are connected to one another in cascade, is capable of processing two asynchronous requests of write and read in parallel, while the cascade-connection structure of the self-synchronous data transmission lines 811-813 deepens the pipeline so that the delay time would be increased in simple proportion to the depth of the pipeline.
In this connection, although intended for use other than the insertion into a self-synchronous pipeline to reinforce the buffer capacity, there has been disclosed, as a similar technique, an asynchronous FIFO memory device (Japanese Patent Laid-Open Publication 2000-11636). This asynchronous FIFO memory device is a FIFO memory device for performing data input and output asynchronously with external devices.
However, this related-art asynchronous FIFO memory device, which is placed intermediate between external write processor and read processor, is purposed to passively respond to write requests or read requests transmitted from those active processors. As a result of this, the asynchronous FIFO memory device is incapable of spontaneously generating a transfer request delay time simply proportional to the depth of the pipeline, is incapable of processing asynchronous requests of write and read in parallel while ensuring normal operations in a critical state in the case where the FIFO memory device is emptied or where there is no empty space left or other cases. Furthermore, in this related art technique, the asynchronous FIFO memory device will not execute data output until it receives an output request from an external processor, so that the FIFO memory device is incapable of spontaneously generating a data transfer request. From these and other constraints, it is difficult to insert the asynchronous FIFO memory device into a self-synchronous pipeline.